Certain integrated circuit microprocessors have long included an internal program, known generally as microcode, which executes external instructions provided by the user. The microcode is stored in an internal memory array. The microprocessor executes the microcode through logic including a program counter which accesses into the microcode memory array. The program counter logic receives an external instruction and then accesses a microcode entry or jumps to a microcode routine to execute the external instruction. The program counter logic includes mechanisms for waits, conditional jumps, and sequencing of instructions stored in the microcode, also known as microinstructions or simply instructions. The microprocessor stores data in internal registers, known collectively as the execution unit, and moves data internally using data paths. In addition, the microprocessor has hardware for performing arithmetic instructions, such as additions, multiplications, shifts, and the like.
When the program counter logic accesses an entry in the microcode, it provides a data element, known as a microinstruction, which includes fields defining hardware to be enabled, data to be moved, etc. The fields are encoded, and a decoder is necessary to convert the field into control signals which enable and disable the hardware for operation. When the user provides an external arithmetic instruction, the microcode causes data to be moved via the internal data paths to the arithmetic hardware and activates appropriate portions of the arithmetic hardware to perform the external instruction.
For example, when the microcode provides a multiply microinstruction, fields in the microinstruction cause the operands to be moved via the internal data paths and to be provided as inputs to a hardware multiplier. Conventional hardware multipliers, such as Booth's multipliers and array multipliers, are known to provide high speed operation and are frequently used in microprocessor design. It is important to include a high-speed multiplier in microprocessor designs because microprocessors typically consume a large amount of time executing such instructions. However, the high-speed multipliers also consume much power and thus present a limitation to the operation of microprocessors which are required to operate in low-power environments, such as battery-backup systems. In addition, some environments such as digital signal processing in telecommunications systems rely on algorithms which are computation-intensive, requiring a large number of multiply instructions.
Accordingly there is provided, in one form, a method for performing multiply and accumulate instructions with reduced power, the multiply and accumulate instructions performed between first and second operands. A first multiply and accumulate instruction is detected when the first operand has a value of either positive one or negative one. A previous result is provided as a first input to an arithmetic logic unit. The second operand is provided as a second input to the arithmetic logic unit. The arithmetic logic unit is enabled for either addition or subtraction respectively in response to a positive or a negative value of a sign bit of the first operand. The arithmetic unit is then activated, and an output of the arithmetic logic unit is provided as a result of the first multiply and accumulate instruction. A second multiply and accumulate instruction is detected when the first operand does not have a value of either positive one or negative one. The first and second operands are provided as first and second inputs to a multiplier/adder. The previous result is provided as an addition input to said multiplier/adder, the multiplier/adder is enabled, and the output of the multiplier/adder is provided as the result of the second multiply and accumulate instruction.